Method for reducing effects of electrical noise in an analog-to-digital converter
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United States of America Patent
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May 24, 1988
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N/A
app pub date -
Oct 7, 1986
filing date -
Oct 7, 1986
priority date (Note) -
Expired
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Abstract
Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.
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