Apparatus and method for reducing write recovery time in a random access memory
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United States of America Patent
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May 10, 1988
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N/A
app pub date -
Dec 18, 1985
filing date -
Dec 18, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An apparatus for reducing the write recovery time of a memory during a write operation is responsive to the detection of a write enable signal for causing the data being written into a selected memory cell to be immediately coupled out on the memory's corresponding output data line independent of the speed at which the data is actually written into the memory cell. The state of a cache memory element is set to reflect this data state such that when the write enable signal goes off, the cache memory element maintains the present state of said output data line. The cache memory element is overridden as the corresponding memory cell reaches a steady state condition at the end of the write operation.
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