Memory address control apparatus with separate translation look aside buffers for a data processor using a virtual memory technique
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United States of America Patent
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Feb 23, 1988
Issued Date -
N/A
app pub date -
Dec 24, 1986
filing date -
Dec 14, 1979
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory control apparatus for a data processor using a virtual memory technique includes two cache memories one for storing a portion of the instructions located in the main memory (MMU), the other for storing a portion of the operand data located in main memory. A separate translation look aside buffer (TLB) is connected to each cache memory, with the TLB connected to the cache memory storing instructions operating to translate logical addresses to real addresses in the MMU storing instructions, while the TLB connected to the cache memory storing operand data operating to translate logical addresses to real addresses in the MMU storing operand data.
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