Dynamic RAM refresh circuit
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United States of America Patent
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Feb 2, 1988
Issued Date -
N/A
app pub date -
Jul 1, 1985
filing date -
Jul 7, 1982
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A dynamic RAM refresh circuit provides the interface for timely refresh of up to 64K of RAM memory while simultaneously providing for minimal disruption of a CPU's access of that RAM memory. Circuitry is also provided to permit interlock control for timeshared access of the RAM memory on a shared basis with the refresh circuit.
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