Clocked logic delay device which corrects for the phase difference between a clock signal and an input binary signal
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United States of America Patent
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Jan 12, 1988
Grant Date -
N/A
app pub date -
Dec 24, 1984
filing date -
Dec 29, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A clocked logic circuit operates in synchronism with a clock and is supplied with an input binary signal asynchronously with the clock for issuing an output binary signal. A phase detector circuit produces a phase difference signal indicating into which of k divided phase regions of one period of the clock falls, the phase difference between the input binary signal and the clock. The phase difference signal is delayed by a matching delay means for a delay approximately equal to a delay of the clocked logic circuit. An output binary signal from the clocked logic circuit is given a delay corresponding to one of the k phase regions designated by the delayed phase difference signal, and the delayed output binary signal is issued to an output terminal.
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