State sequence dependent read only memory
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United States of America Patent
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Dec 29, 1987
Issued Date -
N/A
app pub date -
Oct 17, 1986
filing date -
Dec 7, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The addresses of firmward (ROM) being interrogated to ascertain data are continuously monitored. Selected key addresses are recognized by address detection means. Timing means is then actuated to count a preset number of address accesses, system clock cycles, or other suitable timing means. A substitute address is provided to the firmware when the timer counts down. If the incoming address is in the correct sequence then the substituted address will be the same as the incoming address and correct data will be provided by the ROM. Otherwise, incorrect data will be provided. Alternately, after countdown the incoming address can be compared with the expected incoming address. If the comparison indicates identity then the incoming address can be supplied to the firmware. Otherwise, an incorrect substitute address can be provided to the input of the firmware or incorrect substitute data can be provided on the output of the firmware. In all versions correct data will only be provided if the firmware is interrogated in the correct address sequence.
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