Self-calibration method for capacitors in a monolithic integrated circuit

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United States of America Patent

PATENT NO 4709225
SERIAL NO

06809530

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method for adjusting capacitances in a monolithic integrated circuit wherein it is desirable that the capacitances form a binarily-weighted sequence of values includes sequentially-connecting trim capacitors in parallel with a primary capacitor and determining as each trim capacitor is connected, whether the resultant parallel capacitance is larger or smaller than that of a reference capacitance. If the resultant capacitance is too large, the trim capacitor is disconnected, but otherwise is left connected. The process is repeated until each trim capacitor has been tried. For the purpose of adjusting the capacitance of the next-largest capacitance, the final resultant capacitance is connected in parallel with the reference capacitance to form a new reference capacitance. The procedure is then repeated with the next-largest primary capacitor until the final resultant capacitance associated with each primary capacitor has been adjusted. In another aspect of the invention, capacitance-adjustment steps are sequentially interleaved with analog-to-digital conversions in an analog-to-digital converter.

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Patent Owner(s)

Patent OwnerAddress
CIRRUS LOGIC INC800 WEST SIXTH STREET AUSTIN TX 78701

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Callahan, Michael J Austin, TX 14 491
Welland, David R Austin, TX 151 3701

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