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Abstract

A semiconductor memory device has a semiconductor substrate with a first semiconductor region of one conductivity type in the substrate. A second semiconductor region of the opposite conductivity type is formed in the first semiconductor region. A third semiconductor region of the opposite conductivity type is arranged to be in contact with the first semiconductor region. A fourth semiconductor region of the one conductivity type is formed in the third semiconductor region. A fifth semiconductor region of the one conductivity type, within the semiconductor substrate, has a concentration which is higher than the impurity concentration of the first semiconductor region and is provided under the third semiconductor region. A continuous gate electrode is provided via a gate insulating layer formed on the surface of the first semiconductor region and on the surface of the third semiconductor region. The first, second and third semiconductor regions and the gate electrode form a first insulated-gate field effect transistor. The second, third and fourth semiconductor regions and the gate electrode serving as a second insulated-gate field effect transistor.

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First Claim