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Abstract

A method for fabricating thin-film multilayer interconnect signal planes for connecting semiconductor integrated circuits is described. In this method, a first pattern of thin-film metallic interconnect lines is formed on a surface of a substrate. Then a first dielectric layer is formed over the entire surface of the substrate covering the pattern of thin-film metallic interconnect lines. A portion of the dielectric layer is then removed to expose the thin-film metallic interconnect lines so that a series of trenches is formed above each interconnect line. The interconnect lines are then electroplated to form a series of thicker metal interconnect lines such that the thicker metal interconnect lines and the dielectric layer form a substantially planer surface. This process can then be repeated in its entirely to form a plurality of interconnect signal planes. In the preferred embodiment, metallic vias are provided between each layer of metallic interconnect lines for electrical connection purposes.

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First Claim