Fabricating a CMOS transistor having low threshold voltages using self-aligned silicide polysilicon gates and silicide interconnect regions
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United States of America Patent
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Nov 3, 1987
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N/A
app pub date -
Jan 9, 1985
filing date -
Jan 10, 1984
priority date (Note) -
Expired
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Abstract
The method provides for the formation of a layer of metal silicide on the gate layer of polycrystalline silicon and, for each transistor of the CMOS pair, the simultaneous doping of the active regions and the gate polycrystalline silicon. In the structure produced by this method, the gate electrodes are of polycrystalline silicon covered by metal silicide and the gate electrode of the n-channel transistor is doped with n-type material, while the gate electrode of the p-channel transistor is doped with p-type impurities. This enables the production of low threshold voltages for both transistors even in the case of very high integration densities.
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