Method of making tri-well CMOS by self-aligned process

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 4697332
SERIAL NO

06779388

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A semiconductor structure having at least three types of wells which may be of different doping levels and methods of manufacturing such a structure, are disclosed. In one method, regions which will become active devices are protected with a nitride layer as the associated well-regions are implanted. In another method, previously implanted wells are covered with thick oxide which in combination with the nitride layer provides automatic alignment of adjacent wells. In yet another method, implanted wells are covered with oxide while a last well is implanted with this last well being defined by both thick oxide and photoresist. All methods avoid a masking step and avoid the need for aligning the edge of a later photoresist mask with the edge of an earlier photoresist mask. The structures formed by these methods may have heavily-doped P wells, heavily-doped N wells, and lightly-doped P or N wells, or both, for forming higher breakdown voltage devices on the same chip with lower breakdown voltage devices.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
AMI SEMICONDUCTOR INC2300 BUCKSKIN ROAD POCATELLO ID 83201

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Batra, Tarsaim L Cupertino, CA 5 339
Joy, Richard C Los Gatos, CA 4 179

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation