Logic analyzer
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United States of America Patent
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Sep 22, 1987
Grant Date -
N/A
app pub date -
May 24, 1985
filing date -
May 28, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Logic output data of a plurality of channels simultaneously obtained from a circuit under test are sequentially input in a memory, and after inputting a predetermined amount of such data, they are compared with corresponding expected values. The input data are divided into blocks, each including a plurality of data. Whether a mismatch is present in the comparison results for each block is indicated by a respective block element, and such block elements are displayed in a predetermined arrangement. It is also possible to provide a conventional list display including the input timing corresponding to the comparison results in which a mismatch is present.
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