Memory cell leakage detection circuit
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United States of America Patent
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Aug 4, 1987
Grant Date -
N/A
app pub date -
Nov 14, 1985
filing date -
Nov 14, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A circuit for detecting a short circuit in a SRAM memory cell (10) includes means for connecting the nodes (21, 23) of the memory cell to the gates of a pair of pulldown transistors (66, 68). The pulldown transistors perform a level-shifting function to produce a voltage pattern that has one high node and one low node (72, 74) for a normal cell and two intermediate voltage nodes for a shorted cell. A following logic circuit (76) responds to the voltage pattern to produce an output voltage that has one value when the cell is functioning correctly and another value when the cell is shorted.
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