Importance

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Abstract

A synchronizing gate signal is generated in synchronism with an input signal or a clock signal, and first and second gates are opened by the synchronizing gate signal. The input signal having passed through the first gate is counted by a first counter circuit, and the clock signal having passed through the second gate is frequency-divided by a divide-by-10.sup.n frequency divider. An output from the frequency divider is counted by a second counter means. The synchronizing gate signal is generated under the control of a control circuit, and is prevented from being generated when the output from the frequency divider is applied to the control circuit. The n in the frequency-division ratio 1/10.sup.n of the frequency divider and a maximum count P of a third counter circuit are determined from a count of the third counter circuit, a preset measurement accuracy, and a period of the clock signal at the time one output is produced from the frequency divider, the n being set in the frequency divider. The control circuit is caused to generate the synchronizing gate signal. When the output from the frequency divider is obtained, the count is picked up from the first counter circuit and the synchronizing gate signal is generated again in a repetitive process. Each time the output from the frequency divider is obtained, an average frequency is calculated from the counts of the first counter circuit and the second counter circuit. Until the count of the second counter circuit reaches P, a display indicates that a displayed average frequency has the preset measurement accuracy.

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First Claim