Method for planarizing multilayer semiconductor devices

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United States of America Patent

PATENT NO 4666553
SERIAL NO

06770275

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In accordance with the present invention a method for forming an insulating layer over a substrate surface comprises providing first and second raised portions extending from the substrate surface, the first and second portions extending distances X.sub.1 and X.sub.2 respectively, and X.sub.2 being greater than X.sub.1. An insulating layer of thickness T.sub.3 is deposited over the surface so as to conform to the topography of the substrate surface and raised portions and a flowable layer is then deposited over the insulating layer. The flowable layer is next flowed so as to yield a substantially planar surface and then thinned until that portion of the insulating layer that overlies the second portion is exposed. The flowable layer and the exposed surface of the insulating layer are then simultaneously thinned so as to remove a greater thickness of flowable layer than insulating layer. The thinning is stopped when that portion of the insulating layer that overlies the first portion is exposed. At this point the exposed insulating layer is thinned until a thickness D.sub.1 overlies the first portion and a thickness D.sub.2 overlies the second portion. Thickness T.sub.3 over the substrate surface is not reduced. This thinning is performed such that .vertline.D.sub.1 -D.sub.2 .vertline., .vertline.(D.sub.1 +X.sub.1)-T.sub.3 .vertline. and .vertline.(D.sub.2 +X.sub.2)-T.sub.3 .vertline. are within predetermined ranges.

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Patent Owner(s)

Patent OwnerAddress
MICRON SEMICONDUCTOR INCPATENT DEPARTMENT MS 507 2805 E COLUMBIA ROAD BOISE ID 83706

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bibby, Jr Thomas F A Plainsboro, NJ 5 148
Blumenfeld, Martin A Tequesta, FL 3 41

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