Bit line gain circuit for read only memory
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United States of America Patent
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-
Apr 28, 1987
Grant Date -
N/A
app pub date -
Nov 20, 1984
filing date -
Nov 20, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A ROM memory circuit featuring a bit line gain circuit to the output thereof, effective for establishing isolation of bit and output lines, reduction of bit line voltage swing, VREF level tracking and bit line select circuitry performing a logical OR between two adjacent column select signals with no more than three transistors and effective for generation of a sinking current to maximize the slew rate of the output signal nodes.
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