Data capture logic for VLSI chips
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United States of America Patent
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Apr 21, 1987
Grant Date -
N/A
app pub date -
Apr 15, 1985
filing date -
Apr 15, 1985
priority date (Note) -
Expired
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Abstract
A circuit means for detecting data errors in VLSI processing circuits at the earliest point such an error occurs in the processing stream or (in different modes) at any selected point therein, and for providing the prior operands and faulty (intermediate) output data together with an indication of what is wrong with the data. Described are registers and/or means for controlling the mode of the circuitry, error detection means (being, for example, parity check circuits), and an output means for providing the output in an organized way responsive to the controlling means and the output of the error detecton means. The method of using such a circuit is inherent in the disclosure.
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