Sense amplifier bit line isolation scheme
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United States of America Patent
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-
Mar 17, 1987
Grant Date -
N/A
app pub date -
Feb 11, 1985
filing date -
Feb 11, 1985
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In a CMOS ROM memory arrangement, the use of the least significant column address bit to perform the dual function of even/odd bit line select and the disconnection of the selected bit line (17' and 17') from the sense amplifier (66) driven, in order to reduce its capacitive load, prior to the time of latching the information into the sense amplifier (66).
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