Error-correcting circuit having a reduced syndrome word
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United States of America Patent
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Mar 10, 1987
Grant Date -
N/A
app pub date -
Dec 26, 1984
filing date -
Dec 26, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An error-correction circuit for correcting up to one error in an M-bit data field having the conventional number K parity bits associated with it uses a syndrome word having K-1 bits. The data elements are ordered sequentially and the K-1 bit syndrome word points to errors in the data only, not to errors in the parity bits. One of the data addresses in the field is reserved as a no-error flag and a Kth parity check bit associated with the syndrome word flags an error in the parity bits.
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