Multi-level priority micro-interrupt controller
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United States of America Patent
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Jan 13, 1987
Grant Date -
N/A
app pub date -
Jan 17, 1984
filing date -
Jan 17, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A multi-level priority micro-interrupt controller for a micro-program controlled computer handles a plurality of interrupt signals at a plurality of levels of priority, wherein only one interrupt signal for each level of priority may be active at any moment. When an interrupt occurs which has a higher priority than that of the interrupt currently being handled, the control store address of the next instruction to be executed is stacked and the interrupt handler subroutine for the higher priority interrupt is initiated. When an interrupt occurs which has a lower priority than that of the interrupt currently being handled, it is queued. After an interrupt has been handled, the stack is popped and execution is resumed at the control store address at the top of the stack. The control store address of the interrupt handler subroutine for a particular interrupt is decoded from the interrupt signals in two parts, the second part also being used to control the branching to the interrupt handler subroutine.
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