Semiconductor memory test equipment
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United States of America Patent
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Dec 23, 1986
Grant Date -
N/A
app pub date -
May 15, 1985
filing date -
May 23, 1984
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor tester in which an address is generated by a test pattern generator in synchronism with an operating clock from a timing generator, the address is applied to a memory under test, and a check is made to determine if the power source current to the memory under test is larger than a predetermined value. A current value deciding circuit is provided, by which the power source current value is detected, and it is decided by a comparator whether the detected current value is greater than the predetermined value or not. The decision result is output at the timing of an output timing signal from the timing generator.
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