Analog multiplier with improved linearity
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United States of America Patent
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Feb 25, 1986
Grant Date -
N/A
app pub date -
Apr 2, 1984
filing date -
Apr 2, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An analog multiplier circuit for multiplying X and Y input voltage signals and using two differential amplifiers to produce a multiplied output, in which separate pairs of transistors provide base drive currents to the amplifier transistors, one pair being associated with each amplifier. Trimming voltages are applied between the bases of each transistor pair to independently adjust the base voltage offsets. Nonlinearities between the multiplier output and the X input are reduced by appropriate trimming of the transistor base voltage differentials. Each of the differential amplifier transistors has a common base connection with a matching transistor that carries a current which is complementary to the amplifier transistor current with respect to the Y input signal, thereby reducing output nonlinearities with respect to the Y input signal by making the total base drive currents of both transistors substantially independent of the Y voltage signal. Separate current sources also supply the standing base currents for the transistors of one of the amplifiers, thereby correcting for static imbalances in the base drive circuitry.
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