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Abstract

A logic regulation circuit for regulating the frequency dividing ratio of a variable frequency divider of an electronic timepiece comprises a first switch group having a plurality of ON and OFF switching states representative of different frequency rates and a second switch group having a plurality of ON and OFF switching states representative of frequency rate adjustment values. A first set of memory circuits is connected to the first switch group for memorizing the ON-OFF information thereof, and a second set of memory circuits is connected to the second switch group for memorizing the ON-OFF information thereof. A calculation circuit is connected to the first and second sets of memory cirucits for receiving the information content thereof and for adjusting the frequency rates represented by the information content of the first memory circuits in accordance with the frequency rate adjustment values represented by the information content of the second memory circuits to produce corresponding frequency rate signals suitable for regulating the frequency dividing ratio of the variable frequency divider. The calculation circuit includes a control signal generator for producing control signals according to the frequency rate adjustment values set by the second switch group, and logic circuitry for increasing or decreasing the frequency rates set by the first switch group in response to the control signals.

First Claim