Importance

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Abstract

An improved scannable latch circuit allows its output to be monitored during effectively 100% of the system clock cycle. The circuit further provides dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift-register output. A computer system, in which the scannable latch circuit is used, in conjunction with combinatorial logic and error detection circuitry, may thus monitor the latch output, which is not loaded down by the shift register output, for error detection and other purposes without having to slow down the system operating speed. A preferred embodiment of the scannable latch circuit includes first, second, and third latch elements. When operating a latch circuit, the first latch element operates as the 'master' and the second latch element operates as the 'slave' of a master/slave latch circuit. When operating as a shift register circuit, shift-in data is coupled to the second latch element, and this second latch element operates as the 'master' and the third latch element operates as the 'slave' of a master/slave latch through which data is selectively shifted by appropriate clock signals.

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First Claim