Reduction of contact resistance in CMOS integrated circuit chips and the product thereof
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United States of America Patent
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May 7, 1985
Grant Date -
N/A
app pub date -
Aug 31, 1983
filing date -
Aug 31, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A process for forming the openings (vias) in the glass layer of complementary metal oxide semiconductor (CMOS) integrated circuit chips is presented. The pattern of openings is applied to the glass layer using conventional resist/mask techniques. A plasma is used to remove the glass, and the silicon dioxide layer, if there is one, to expose a portion of the N+ and P+ circuit elements. Decreased conductivity of the crystalline lattice structure of the N+ material, caused by exposure to the plasma, appears as an added resistor between the N+ material and the metallization layer. The added resistance is reduced to acceptable levels before the metallization layer is applied by placing the chip in an inert gas atmosphere at an appropriate elevated temperature for an appropriate time.
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