Technique of producing tapered features in integrated circuits

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United States of America Patent

PATENT NO 4514252
SERIAL NO

06442545

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A technique is presented for producing tapered walls. In accordance with the disclosed technique, a mask is generated on a workpiece and the workpiece is etched through the mask to replicate the mask pattern into the mask. These steps result in walls at the boundaries of the replicated mask features. In many such processes, these walls are either substantially vertical or have an overhanging portion of the walls. In order to taper the walls, the upper corners of the walls are cut away to remove the overhang or to cut the corner back an additional amount to produce a controlled amount of taper.

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Patent Owner(s)

Patent OwnerAddress
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE LTDSINGAPORE SINGAPORE SINGAPORE CITY SINGAPORE

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Roland, James P Ft. Collins, CO 6 78

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