Test fixture for providing electrical access to each I/O pin of a VLSI chip having a large number of I/O pins
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 12, 1985
Grant Date -
N/A
app pub date -
Sep 30, 1982
filing date -
Sep 30, 1982
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A VLSI chip tester for defining and performing functional tests, delay tests, and DC parametric tests on VLSI chips. The VLSI chip under test is mounted to a paddle card which, in turn, is detachably held under pressure against a circuit board mounted in a test fixture. A connector is sandwiched between the paddle card and circuit board. The connector has insulated, spaced-apart conductors that are orthogonal to the paddle card and circuit board, and that provide electrical contact between each pin of the VLSI chip under test and a corresponding pad on the circuit board. Shift register circuits mounted to the circuit board provide a single stage corresponding to each I/O pin of the device under test. Each stage may function as an input or output device. A computer or computers are coupled to the shift register circuits through appropriate cabling and driver/receiver/termination circuits. Test data to be sent to or from the computer may be shifted serially into or out of the shift register circuits. Similarly, test data to be sent to or from the device under test may be shifted in parallel into or out of the shift register circuits. A self-test capability is provided.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully