Memory system including RAM and page switchable ROM
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United States of America Patent
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Nov 27, 1984
Grant Date -
N/A
app pub date -
May 31, 1983
filing date -
May 31, 1983
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory system for use in a video game system or the like that has a limited number of signal lines for communicating address signals and a data bus, includes random access memory (RAM) to augment that contained in the game console in addition to plural segments of read only memory (ROM). A first decoding circuit is coupled to the data bus and to the signal lines that communicate address signals to the ROM segments, and in response to detection of a predetermined address and a predetermined status of selected data lines produces a signal that selects one of the plurality of ROM segments of memory locations. A second decoding circuit is coupled to a selected group of the address signal lines, and also to a segment of the memory unit set aside for random access memory (RAM) to which the others of the address signal lines are also coupled. When a predetermined address is communicated, the first decoding circuit is inhibited and the second decoding circuit couples an instruction signal to the RAM segment to either write data to or read data from a memory location addressed by the others of the address lines.
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