Importance

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Abstract

There is disclosed a frequency monitor circuit, for monitoring AC power frequency for example, in which a gate is provided for a stable oscillator and frequency divider circuit which is responsive to the frequency divided monitored signal and a flip-flop circuit to produce a fixed reference period signal equal to a predetermined number of cycles of the oscillator commencing at the beginning of a full cycle of the monitored signal; a two-stage timer which determines the tolerance for the monitored signal frequency and is adjustable is provided with signals from the monitored signal divider circuit and the fixed reference period circuit and arranged so that the end of the reference period or the end of the divided monitored signal cycle, whichever occurs first, will start the timer. Its output latches a pair of flip-flop circuits acting as decoders which are respectively supplied with the state of the frequency divided monitored signal and the fixed reference period signal. If both have ended and changed state, the monitored signal is determined to be within frequency tolerance; if the frequency divided monitored signal has not changed state the frequency is low; if the fixed reference period signal has not changed state the frequency is high; high and low indicators are provided and a relay driver is operated in response to a within-tolerance condition. A double frequency detector circuit produces an inhibiting signal which resets the low frequency decoder flip-flop and prevents a false low frequency signal for monitored signal frequencies about or more than double the center frequency. One stage of the two stage timer is caused to have a negligible time delay by a signal fed from the out-of-tolerance output of the decoder circuits so that entry into within tolerance condition is more restricted than maintenance of within tolerance condition thus preventing vacillation between the two conditions in borderline cases.

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First Claim