Lookahead addressing in a pipeline computer control store with separate memory segments for single and multiple microcode instruction sequences
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United States of America Patent
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Jun 28, 1983
Grant Date -
N/A
app pub date -
Oct 20, 1980
filing date -
Oct 20, 1980
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The microinstructions controlling a pipeline processor are held in a control store that is partitioned into two microcode memory banks. The invention can support three modes of sequencing; single microinstruction, sequential multiple microinstructions, and multiple microinstructions with conditional branching. When a conditional branch is performed, the branch not taken path is assumed and if true, the microinstruction following the branch is executed with no delay. If the branch is taken, the guess is purged and following a one clock delay, the branched to microinstruction is executed. The invention supports these sequencing modes at the maximum pipeline rate, since the only logic between registers is the memory chips.
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