Apparatus for converting serial input sparse vector format to parallel unpacked format for input to tandem arithmetic logic units
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United States of America Patent
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Feb 1, 1983
Grant Date -
N/A
app pub date -
Sep 29, 1980
filing date -
Sep 29, 1980
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Apparatus is disclosed for processing sparse vectors in a tandem or parallel processing environment. Sparce vectors are those vectors stored in memory with their zero-valued operands deleted. They have a corresponding order vector of bits whose state indicates the order of zero and non zero operands in a corresponding expanded vector. The apparatus fetches the order vectors n bits at a time, n corresponding to the number of tandem processors, and counts the number of one bits. This number of operands is then fetched from memory. The apparatus aligns and orders the fetched sparse vector operands, inserts zero operands where appropriate, and forwards the resulting portion of the expanded vector to the tandem processors for processing.
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