Multilevel PWM inverter
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 10, 1982
Grant Date -
N/A
app pub date -
Sep 14, 1981
filing date -
Sep 14, 1981
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The multilevel inverter includes a voltage divider which when connected across a dc source E.sub.D, provides voltage at terminals having values between +E.sub.D to -E.sub.D. A first and a second set of thyristors pairs are connected between the positive or negative terminals, respectively, and a load terminal for applying selected voltage levels to the load. Any thyristor pair in these sets may be turned-off by firing the thyristor pair at the next highest voltage level. However, the main thyristors which are connected to the +E.sub.D or -E.sub.D terminal is turned-off by a commutation circuit. This circuit includes a single capacitor maintained at zero voltage and subjected to an oscillating voltage during the commutation cycle to turn-off the conducting main thyristor. Such an inverter can easily provide a waveform having a series of pulses at one or more voltage levels thereby eliminating harmonics in the output.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully