Error checking circuit
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United States of America Patent
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Jul 27, 1982
Grant Date -
N/A
app pub date -
Sep 8, 1980
filing date -
Sep 8, 1980
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An error checking circuit is provided for a digital transmission system having a dual, redundant, bus structure. The error checking circuit generates a two rail logic output having complementary states in the absence of an error, and non-complementary states in response to an error on the buses. The circuit is also self-checking in that internal failures are transmitted to the output as an error indication. The circuit is actively exercised in the absence of an error to prevent silent failures. The circuit can identify which of the buses has failed, for the most common types of failures.
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