Address pattern generator for testing a memory
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United States of America Patent
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Nov 10, 1981
Grant Date -
N/A
app pub date -
Oct 10, 1979
filing date -
Oct 11, 1978
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An address pattern generator for use in a test pattern generator for generating various patterns for testing semiconductor memories. A plurality of fixed registers for storing an initial value at the start of a test, a boundary value and an operand indicating the amount of change of an address are provided in common to at least two address operating circuits. The address operating circuits are each capable of taking therein the content of a desired one of the fixed registers. At least two output registers are provided, which are each capable of taking therein the operation result of a desired one of the address operating circuit. The contents of these output registers are supplied as addresses to a memory under test.
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