Power-on-reset circuit with power fail detection
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United States of America Patent
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-
Apr 7, 1981
Grant Date -
N/A
app pub date -
Jun 12, 1979
filing date -
Jun 12, 1979
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A power-on-reset circuit with power fail detection, comprises a supply voltage V, and a voltage divider comprising two series resistors connected between V and the ground. The junction between the two resistors is connected to the (+) terminal of a voltage comparator. The junction is also connected through a diode to the (-) terminal of the comparator. The (-) terminal is also connected to ground through a capacitor and resistor in parallel. A resistor and compacitor in series are connected between V and ground and the junction between the resistor and the capacitor is connected to the output of the comparator, and also to the input of an inverting gate. The output of the inverting gate is the power-on-reset terminal.
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