Signal strength detecting circuit
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United States of America Patent
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Jan 27, 1981
Grant Date -
N/A
app pub date -
Feb 6, 1979
filing date -
Mar 29, 1978
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An input signal is applied to a first limiting amplifier circuit, and an output of the first limiting amplifier circuit is applied to a second limiting amplifier circuit. An output of the second limiting amplifier circuit is applied to a third limiting amplifier circuit. The output signal of the first limiting amplifier circuit is applied to a first detector circuit, the output signal of the second limiting amplifier circuit is applied to a second detector circuit, and the output signal of the third limiting amplifier circuit is applied to a third detector circuit. Bias means for stipulating the bias states of the first, second and third detector circuits are coupled to the third detector circuit. An output signal of the third detector circuit is applied to the second detector circuit as a bias signal, and an output signal of the second detector circuit is applied to the first detector circuit as a bias signal. An output signal of the first detector circuit exhibits a level corresponding to the sum among the output signals of the first, second and third limiting amplifier circuits.
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