MEMORY ARRAY SOURCE/DRAIN ELECTRODE STRUCTURES
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United States of America
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Issued Date -
Apr 10, 2025
app pub date -
Dec 18, 2024
filing date -
Dec 18, 2024
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Abstract
A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.
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