CLOCK BUFFER
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United States of America
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Issued Date -
Apr 10, 2025
app pub date -
Oct 25, 2024
filing date -
Oct 25, 2024
priority date (Note) -
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Abstract
A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the input clock signal.
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