Importance

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Abstract

A semiconductor module according to the present disclosure comprises a high potential side drive circuit and a low potential side drive circuit. The high potential side drive circuit includes: first reception terminals to receive a first data signal, an enable signal, and a first clock signal; a first shift register; and a first output terminal to output the first clock signal to the low potential side drive circuit as a second clock signal. The low potential side drive circuit includes: second reception terminals to receive a second data signal, the enable signal, and the second clock signal; a second shift register, and a second output terminal to output the second data signal held in a flip-flop of a last stage of the second shift register to the high potential side drive circuit as the first data signal.

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First Claim