METHODS OF FORMING MEMORY STRUCTURES FOR THREE-DIMENSIONAL NONVOLATILE MEMORY

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20250118547A1
SERIAL NO

18906944

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Abstract

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According to an aspect, a method of forming a memory structure for a 3D NAND flash memory includes forming a layer stack over a substrate, forming first recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back gate layers of the layer stack from the memory hole, and forming a lateral memory stack in each first recessed areas, by depositing a blocking oxide and, subsequently, a charge trap material. The method also includes forming second recessed areas in the sidewall by laterally etching back the inter-gate spacer layers from the memory hole and forming dummy layers in the second recessed areas. The method also includes lining the sidewall of the memory hole with a liner layer, subjecting the dummy layers to a thermal treatment process adapted to convert each dummy layer into an air gap structure, and forming a tunneling oxide layer in the memory hole, along the liner layer, and a channel layer along the tunneling oxide layer.

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Patent Owner(s)

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IMEC VZWKAPELDREEF 75 LEUVEN 3001

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Armini, Silvia Heverlee, BE 17 292
Rachidi, Sana Leuven, BE 2 0
Rosmeulen, Maarten Gent, BE 25 137
Van, den Bosch Geert Kessel-Lo, BE 3 2

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