NON-VOLATILE MEMORY WITH CURRENT DETECTION CIRCUIT
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United States of America
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Issued Date -
Apr 10, 2025
app pub date -
Oct 5, 2023
filing date -
Oct 5, 2023
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Abstract
A memory system implemented on one or more die includes a power input line for the one or more die, a current detection circuit connected to the power input line such that the current detection circuit is configured to indicate whether current at the power input is greater than a reference current, and a control circuit connected to the power input line and the current detection circuit. The control circuit is also connected to a non-volatile memory structure comprising a plurality of non-volatile memory cells. The control circuit is configured to sense data from the non-volatile memory structure including lowering a voltage used during the sensing in response to the current detection circuit indicating that current at the power input line is greater than the reference current.
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