FAST TWO-SIDED CORRECTIVE READ OPERATION IN A MEMORY DEVICE
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United States of America
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Issued Date -
Apr 10, 2025
app pub date -
Dec 17, 2024
filing date -
Dec 17, 2024
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Abstract
A memory device includes an array associated with a plurality of wordlines and control logic that causes a first voltage to be applied to a first wordline associated with a selected memory cell, causes a second voltage, having a lower magnitude than the first voltage, to be applied to a second wordline adjacent to the first wordline and associated with a first neighbor memory cell, and causes a third voltage, having a lower magnitude than the first voltage, to be applied to a third wordline adjacent to the first wordline and associated with a second neighbor memory cell. The control logic identifies a first corrective read voltage in response to determining that current flows through the first and second neighbor memory cells and the selected memory cell and causes the first corrective read voltage to be applied to the first wordline during a read operation for the selected memory cell.
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