SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CHIP BONDED TO A CMOS CHIP INCLUDING A PERIPHERAL CIRCUIT
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United States of America
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Issued Date -
Apr 10, 2025
app pub date -
Dec 17, 2024
filing date -
Dec 17, 2024
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Abstract
A semiconductor device includes plural storage portions, plural wirings each extending in a first direction, plural circuits each configured to sense a voltage of a respective one of the plural wirings, and plural pads each provided between one of the wirings and a corresponding one of the circuits. A first circuit and a second circuit among the plural circuits belong to a first group, are adjacent to each other, and are arranged in a second direction intersecting the first direction. A third circuit among the plural circuits belongs to a second group. The first group and the second group are adjacent to each other and arranged in the first direction. The plural pads are adjacent to each other and are arranged in the first direction or a third direction intersecting the first direction and the second direction.
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