APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES
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United States of America
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Issued Date -
Apr 10, 2025
app pub date -
Jun 18, 2024
filing date -
Jun 18, 2024
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Single (1 T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.
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