Importance

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Abstract

An example apparatus includes a data bus including a first portion having a timing domain which is controlled based on a first timing signal and further including a second portion having a timing domain which is controlled based on a second timing signal, and a data transfer circuit coupled to the data bus, the data transfer circuit including a data driver between the first portion of the data bus and the second portion of the data bus and a timing control circuit coupled to the data driver. The timing control circuit includes a variable delay to add an amount of delay to a first control signal to generate a second control signal. The data driver is configured to drive data from the second portion of the data bus to the first portion of the data bus responsive to the second control signal.

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First Claim