SIGNAL GENERATOR FOR CONTROLLING TIMING OF SIGNAL IN MEMORY DEVICE
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United States of America
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Issued Date -
Apr 10, 2025
app pub date -
Dec 17, 2024
filing date -
Dec 17, 2024
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Abstract
A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.
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