Importance

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Abstract

Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

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First Claim