CACHE MEMORY ARCHITECTURE AUGMENTATION FOR 3-DIMENSIONAL (3D) DATA
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United States of America
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Issued Date -
Apr 10, 2025
app pub date -
Oct 5, 2023
filing date -
Oct 5, 2023
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status (Latency Note)
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Abstract
Aspects of the disclosure are directed to reordering a plurality of input block voxel indices in a cache memory. In accordance with one aspect, an apparatus including a create block configured to receive the plurality of input block voxel indices and configured to generate a reordered list based on the plurality of input block voxel indices; and an integrate block coupled to the create block, the integrate block configured to use the reordered list to deliver integrate depth data for generating a plurality of output block voxel indices. In accordance with one aspect, a method including reordering the plurality of input block voxel indices into a plurality of output block voxel indices using a separated set of input block voxel indices; and accessing the plurality of output block voxel indices to provide an augmented cache memory access.
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