Instruction and Micro-Architecture Support for Decompression on Core
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United States of America
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Apr 10, 2025
app pub date -
Nov 14, 2024
filing date -
Nov 14, 2024
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Abstract
Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.
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