Flushing Cache Lines Involving Persistent Memory
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Apr 10, 2025
app pub date -
Dec 19, 2024
filing date -
Dec 19, 2024
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully